FIELD OF THE INVENTION
The present invention relates to a configuration for testing integrated components, having a carrier frame into which test bases for receiving the components can be inserted.
Integrated components and in particular memory components are known to be subjected to final tests to check them for perfect operation, before they are handed over to customers. In order to perform those final tests, carrier frames are used, into which test bases that in turn receive the individual memory components can be inserted.
It has now been found that in such existing configurations, contact failures regularly occur, which leads to a reduced yield in the final tests. The currently used test bases also have an average service life on the order of magnitude of only approximately 10,000 contacting operations. After those 10,000 operations, the test configuration must be dismantled n order to replace the original test bases in the carrier frame.
One example thereof that can be mentioned is memory components in a so-called TSOP housing. At a throughput of 4000 DUTs/hr. (DUT stands for Device Under Test, i.e., the test component), the test bases have to be replaced after approximately one week, which means a loss of at least one hour of production. Such a time loss is extremely undesirable with regard to the mass production of integrated components.